Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
نویسندگان
چکیده
Word level information on the Register Transfer Level (RTL) offers information for efficient guidance of the proof process in formal verification. Therefore several proof techniques with integrated word level support from other research fields can be applied for formal verification of circuit designs as well. The focus of this work is to evaluate the proof techniques Boolean Satisfiability (SAT), SAT Modulo Theories (SMT), SWORD and Constraint Satisfaction Problem (CSP) in the context of formal hardware verification. An estimation of the effort to encode standard circuit elements is given and the advantages and disadvantages of the different encodings is studied. In our experiments we consider equivalence checking problems for circuit designs given on bit and word level.
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